1. Field of the Invention
The present invention relates to testing RAM blocks embedded in an integrated circuit and, more particularly, to internal RAM scan chain testing and RAM scan testing of RAM blocks.
2. Background Art
Certain integrated circuits can have a number of embedded RAM blocks. An example of a 32×32 RAM block is shown, generally indicated at 10, in FIG. 1. All the flip-flops and multiplexers (mux) are inside of the RAM block. All of the inputs 11, except for the clocks (e.g., RCK, WCK), have both a normal functional input as well as a Built In Self Test (BIST) input, which are multiplexed together to drive registers 13. A clock enable pin (CEB), when asserted low, enables a flip-flop 13 to be loaded from the D input pin. Otherwise, the flip-flop does not change state. Thus, the internal registers 13 are updated only when REN/WEN or BIST_REN/BIST_WEN is asserted.
A 64×64 RAM block is similar in structure to the 32×32 RAM block. The address widths are six and the data widths are sixty-four. Additionally, the 64×64 RAM block has a byte write enable (BWEN) function. There are eight BWEN inputs and eight BIST_BWEN inputs that control the writing of the eight bytes within the sixty-four-bit word. These signals are active low, for example, BWEN=8′b1111—0011 will enable the 3rd and 4th bytes to be written into the memory; the other bytes remain unchanged. In certain integrated circuits, the OEN and BIST_OEN inputs are always asserted low, so the DOUT outputs are always driving, and there are sixteen instances of the 32×32 RAM block and eight instances of the 64×64 Ram block for a total of twenty-four RAM blocks.
During manufacturing of an integrated circuit, it is desirable to test for defects inside of each of the twenty-four RAM blocks. It would be preferable to bring the address and data pins of the RAM block out to pins on the chip, so one could have access to the address and data for testing. However, this approach requires a significant amount of pins and wiring to bring the RAM blocks out to chip pins, which is not practical.
Another approach is to rely on a functional test wherein normal activity is run through the chip to hopefully exercise all of the RAM addresses. However, this approach requires significant activity at the chip level in order to exercise all of the RAM addresses and appropriate data patterns.
Furthermore, it is desirable to employ Automatic Test Pattern Generation (ATPG) tools in testing integrated circuits with embedded RAM blocks. These tools build a model of the chip and detect “stuck at” faults, e.g., “stuck at 1”, or “stuck at 0”, monitored at input and outputs of circuits. These tools generate patterns to control an internal point (e.g., set an output of a gate high). In addition, if there is a fault at an internal point, then that fault needs to be propagated to an output point or pin, where the APTG tool can observe that there is an internal fault. Thus, when attempting to drive a pin high and the pin output is stuck at low fault, this condition will be detected by observing an output pin. Typically, the ATPG tools cannot handle setting an address or creating the correct timing sequences on clock pins to change the contents of the RAM and check the output. As shown in FIG. 2, the RAM block 10 is a “black hole” blocking the ability to observe faults propagated to the RAM inputs, and preventing control of RAM outputs, which drive downstream logic.